Processor architecture is the layer least discussed in digital-sovereignty conversations — and possibly the most important, because it defines instrumental dependency at the lowest level of the stack. Every piece of software, every cloud workload, every AI model ultimately runs on a processor's instruction set. Whoever controls that instruction set controls the basic rules of the game.
x86: the Intel-AMD duopoly
The x86 instruction set is proprietary — owned by Intel and AMD on the basis of mutual licensing. A European manufacturer cannot produce an x86-compatible processor without a licence from one of them. The EU has neither an x86 design house nor a manufacturer. This is acceptable as long as the relationship with the U.S. holds — and risky if it does not.
ARM: the licensing model
ARM Holdings (owned by SoftBank, registered in the United Kingdom) licenses the ARM instruction set on a commercial basis. A European manufacturer can design an ARM processor — and SiPearl (France) does this for EuroHPC supercomputers. SiPearl's processor Rhea combines ARM Neoverse V1 cores with custom accelerators — a hybrid approach, not pure RISC-V — and powers Europe's exascale supercomputers Jupiter (Jülich) and LUMI (Kajaani). It is the most advanced European processor design currently in production, but still depends on the ARM licence.
The ARM architecture is growing on the server side: Dell'Oro Group estimates ARM servers reached approximately 15 % of the market in Q2 2025; , Data Center Semiconductors and Components up 44 Percent on AI Hardware Demand in 2Q 2025, According to Dell'Oro Group , 2025-09-11 · link · archived AWS runs over 50 % of its EC2 instances on its own Graviton processors. But the licence remains in non-European hands. After Brexit, ARM Holdings is formally outside the EU.
RISC-V: the open instruction set
RISC-V International maintains an open standard — anyone who wishes can design and manufacture a RISC-V processor without a licence fee. From a sovereignty perspective this is revolutionary: no state can cut another state off from access to the instruction set. In 2026, RISC-V is in commercial production primarily in embedded and IoT segments. For servers and AI accelerators it is in an early stage — but the EuroHPC project DARE (Digital Autonomy with RISC-V in Europe) , DARE — Digital Autonomy with RISC-V in Europe , 2025-03-06 · link · archived funds the development of a European HPC processor based on RISC-V.
Codasip (Brno, Czech Republic) — originally a Czech company, currently in a sale process — is one of the world's key players in RISC-V core design. Codasip develops configurable processor cores; its technology allows the customer to adapt the instruction set to specific applications. For Europe it is strategically important: the loss of Codasip from the European ecosystem would weaken the EU's position in the RISC-V space.
What this means strategically
The EU has three paths in processor architecture:
- Maintain x86 access through transatlantic partnership. Short-term safe, long-term dependent.
- Support ARM-based design. SiPearl Rhea for HPC is an exemplar. Carries licence risk: ARM Holdings is owned by SoftBank, registered in the UK, post-Brexit outside the EU. If geopolitical pressure on ARM intensifies, this dependency activates.
- Invest in RISC-V as long-term insurance for instrumental sovereignty. The DARE project, Codasip, the broader European RISC-V ecosystem.
These three paths are not mutually exclusive. The ideal strategy is parallel, with growing emphasis on RISC-V in the 2026–2030 horizon. Codasip's situation is a near-term test: whether Europe can keep its leading RISC-V design firm in the European industrial ecosystem will be one signal of whether the EU's processor strategy is more than rhetoric.